We are currently partnered with a global leader in advanced MEMS-based programmable semiconductor solutions transforming the timing industry. They are looking to expand their team with an experienced verification engineer to work on the development of MEMS timing ICs.

The Role

As a Senior Verification Engineer, you will be responsible for the development of SV-RNM models for analog and mixed-signal circuits, owning verification plans based on chip/block specifications, and building and maintaining UVM-based environments. You will drive digital-top verification, define SystemVerilog Assertions (SVA), write functional coverage models, execute simulations, and debug testbench failures. Collaboration with design, test, and other verification teams will be essential, as well as reviewing and validating verification results for tape-out sign-off.

Responsibilities

• Develop SV-RNM models for analog and mixed-signal circuits
• Own verification plans based on chip/block specifications
• Build and maintain UVM-based environments (scoreboards, sequencers, monitors)
• Drive digital-top verification and define SystemVerilog Assertions (SVA)
• Write functional coverage models and covergroups
• Execute simulations and debug testbench failures
• Collaborate cross-functionally with design, test, and other verification teams
• Review and validate verification results for tape-out sign-off

Requirements

• 5+ years post-Masters or 8+ years post-Bachelors in semiconductor verification
• Proficiency in SystemVerilog and UVM methodology
• Experience with scripting languages (Python, Perl)
• Strong command of SystemVerilog Assertions (SVA)
• Familiarity with analog schematics and Cadence Virtuoso

If you are interested in this Senior Verification Engineer position, please send a copy of your CV to ts@eu-recruit.com.